1. Field of the Invention
The field of the invention is that of receiving digital signals in devices designed to receive signals transmitted at different source symbol frequencies. The invention concerns in particular multirate modems used in satellite or microwave links, for example.
Accordingly, the invention finds applications in many fields, both civil and military, where it is necessary to receive signals transmitted at at least two different source symbol frequencies.
2. Description of the Prior Art
In an increasing number of applications modems are required to be able to handle a plurality of data rates. In particular, this feature is required for most satellite transmission applications. For example, the IBS (International Business Systems) standard requires modems to be capable of handling a large number of data rates, from 64 kbps up to 2 Mbps.
This requirement for data rate agility naturally increases the complexity of the modems. The transmit and receive filters, whether analog or digital, are no longer fixed but must be variable to track the data rate.
It is also necessary to generate a plurality of clocks that are synchronous or quasi-synchronous with each of the data rates used. Quartz crystal voltage-controller oscillators (VCXO) used in fixed rate modems have to be replaced with much more complex frequency synthesizer devices.
There are already at least three prior art multirate receiver architectures intended to meet these requirements.
FIG. 1 shows a first of these, in the form of a conventional digital modem.
The received signal 11 is first transposed into the baseband by a module 12 supplying in-phase and quadrature signals 13. The in-phase and quadrature signals 13 are then fed to an analog low-pass filter 14. The complex envelope is filtered by means of a bank of analog filters. These are anti-aliasing filters preceding sampling.
The filtered signal is sampled by an analog-digital converter module 15: the filtered complex envelope is sampled using a clock 16 at a frequency which is a multiple of the symbol frequency, synchronized in phase to the received signal. The samples obtained are then digitized by a converter
A pre-filter and decimator module 17 attenuates out-band interference and applies decimation that is varied according to the data rate in order to reduce the oversampling ratio at the input of the channel filter to an integer value that is usually between 2 and 4, as required by the timing estimator.
The channel filter 18 applies the matched filtering needed to obtain good error rate performance. The criterion for optimizing this filter is usually the best compromise between residual intersymbol interference and the noise power at its output.
The filtered signal is passed to a module 19 which corrects its phase in accordance with data supplied by a carrier phase estimator module 110. The phase error is estimated from the channel filter output signal and corrected. The carrier phase estimation and correction techniques are outside the scope of the invention and for this reason will not be described here.
The samples from the pre-filter (or possibly the channel filter) are used in a timing estimator module 111 to estimate the time shift of the received signal 11 relative to the receiver reference (modulo the symbol time). The estimate is filtered and then passed (112) to the oscillator 113, the frequency of which is controlled digitally. Various timing estimation algorithms can be used. Their common feature is that they require an oversampling ratio of the input signal 114 of at least 2.
The digitally controlled oscillator 113 has to supply a set of frequencies 115 that are multiples of the data rate used. It also has a frequency modulation input 112 controlled by the timing estimator 111 for slaving the phase of the clock to the optimal pointing time.
In this type of structure, the number of analog filters in the module 14 depends on the specifications of the interference to be allowed for and whether there is a pre-filter or not.
In a slightly different embodiment the transposition into the baseband can be effected in the digital domain rather than the analog domain. In this case this operation is naturally carried out after analog-digital conversion.
In a second type of prior art modem, shown in FIG. 2, the sampling clock frequency is variable according to the data rate but it is not synchronized in phase. These modems are known as quasi-synchronous interpolation modems. The sampling frequency usually adopted is of the type qF.sub.s +.epsilon. where F.sub.s is the symbol frequency, q is the integer oversampling ratio and .epsilon. is a very small frequency shift, calculated according to the frequency shift specifications of the transmit and receive oscillators.
The modules 12, 14, 15, 17 through 111 are similar to those in FIG. 1 and will not be described again. The essential difference is that the oscillator 21 is no longer controlled in phase by the estimator 111. In other words, this architecture does not have any feedforward loop It has the advantage of eliminating the frequency control input of the oscillator.
The theory of this type of architecture is explained in detail in the article "Digital Filter and Square Timing Recovery" by H. Meyr and M. Oerder (IEEE Transactions on communications--vol. 36, n.sup.o 5, May 1988).
In this architecture, the sampling error is corrected using a digital interpolation filter 22 controlled by the timing estimate 111. Suitable interpolation filters are described by Bucket and Moeneclaey in the article "Symbol synchronizer performance affected by non-ideal interpolation in digital modems" ("Performance de la synchronisation symbolique affectee par une interpolation non-ideale dans les modems numeriques") ICC 94, p. 929 (paper category: synchronization; performance of digital receiver algorithms).
The major drawback of the two architectures described above is that they use a variable frequency oscillator which is a complex, fragile and costly device, especially if it is required to change frequency fast and in small steps.
A third type of modem that may be considered is known as an asynchronous interpolation modem.
FIG. 3 is a generic block diagram of a modem of this kind. The received signal 11 is transposed into the baseband (12) and then passes through an anti-aliasing filter 14. A sampling clock 31 with a fixed sampling period Ts controls a sampler 32 which feeds samples to a matched filter 33. The phase is then corrected (34) under the control of a phase correction module 35.
Finally, the samples are fed through an interpolation filter 36 to a symbol decision module 37. The interpolation filter 36 is controlled by a timing estimator module 38 connected to the outputs of the interpolation filter 36 and the decision module 37.
An architecture of this type, very similar to that of the second type, is described in the article by Bucket already mentioned. The main advantage of this architecture is that the sampling oscillator 31 operates at a fixed frequency. This greatly simplifies the clock generator devices.
In the general case the oversampling ratio (X) becomes a fractional number, X corresponding to the ratio of the sampling frequency to the symbol frequency. The operation of the interpolator 36 is slightly modified as compared to the previous type interpolator (a detailed description is provided in the Bucket article)
In this structure the choice of the oversampling ratio at the interpolator input is the result of a compromise between the complexity of the interpolator, that of the channel filter and the required level of performance. An oversampling ratio greater than 4 enables the use of very simple first order (linear) interpolation with minimal performance degradation, whereas an oversampling ratio close to 2 requires a much more complex interpolator. On the other hand, the computation power required of the channel filter, which is proportional to the oversampling ratio at its output, increases when that of the pre-filter is reduced.
These asynchronous interpolation modems thus have the advantage of using a fixed oscillator. On the other hand, they do have a few drawbacks. In particular, they require a high oversampling ratio, always greater than 2. Thus for a simple (first order) interpolator to be usable, the oversampling ratio at the interpolator input must be at least 4, which requires high signal sampling frequencies, which is costly in high data rate applications.
The interpolator 36 is intrinsically a sub-optimal device and degrades system performance.
What is more, the various filters employed require a high computation capacity, leading to a large size (silicon surface area, for example), high computation time and/or cost, and therefore high manufacturing cost.
One particular object of the invention is to overcome these various drawbacks of the prior art.
To be more precise, one object of the invention is to provide a multirate receive device using a fixed frequency oscillator of reduced complexity compared to prior art interpolation type devices.
Accordingly, an object of the invention is to provide a device of this kind with computation time, computation capacity, size and/or design and manufacturing cost reduced in comparison with prior art devices.
Another object of the invention is to provide a device of this kind that is more accurate than prior art devices. In particular, one object of the invention is to provide a device of this kind which does not degrade performance in the manner associated with an interpolation filter.
A further object of the invention is to provide a device of this kind capable of operating with an oversampling ratio as low as 2 without degrading performance.
An additional object of the invention is to provide a device of this kind able to operate at very high data rates with the facility to change the data rate fast and accurately.